The present invention relates, in general, to flash memory devices and, more particularly, to a method of fabricating a flash memory device, which improves variation in Effective Field Height (EFH).
As memory devices become smaller in size, the surface area of a dielectric layer surrounding a floating gate changes. The surface area changes in relation to the degree that an isolation layer is recessed. The isolation layer is recessed to control the EFH of the isolation layer when the floating gate is formed by a Shallow Trench Isolation (STI) process during fabrication of the flash memory device that is 60 nm or less.
The EFH of the isolation layer varies widely because several processes are performed during fabrication that influence properties of the device. Example processes include a Chemical Mechanical Polishing (CMP) process for forming the isolation layer, a wet cleaning process for removing a hard mask layer, and a wet cleaning process for recessing the top surface of the isolation layer.
Variation in the surface area of the dielectric layer surrounding the floating gate causes variation in the coupling ratio between the floating gate and the control gate. Thus, fatal problems in device operation and performance often result. Example problems include variation in programming speed and interference due to increased capacitance, and a shift in the threshold voltage (Vt) due to cycling.
The EFH of the isolation layer is regulated to prevent damage to the low voltage region of the peri region during formation process of a gate. However, if the EFHs of the isolation layers in the cell region and the peri region are set to the same value, a loading phenomenon occurs due to a difference in the pattern size during an etch process for forming a STI profile of the low voltage region and the gate. Thus, damage occurs due to a difference in the amount in which the isolation layer is recessed. The damage occurs during the etch process when forming the gate.
During the STI etch process of the peri region, an etch target of a tunnel insulating layer depends on the thickness of a gate insulating layer formed in a high voltage region of the peri region, in which the thickness of the insulating layer is the largest. In the low voltage region where the thickness of the tunnel insulating layer is relatively small, the tunnel insulating layer is etched during the etch process of the tunnel insulating layer, and a semiconductor substrate is over-etched. Thus, top corners of a trench become sloped.
The slope profile at the top corners of the trench projects outwardly from the side of the floating gate. Thus, the top surface of the isolation layer is partially removed during the etch process for forming the gate. Consequently, damage occurs due to the removed isolation layer.